1. Field of the Invention
The present invention relates to a video signal processing apparatus. More specifically, the present invention relates to a video signal processing apparatus which includes a time-division multiplex circuit for multiplexing a plurality of video signals so as to record the plurality of video signals by a video tape recorder, and a multi-display circuit for simultaneously displaying a plurality of images on a plurality of monitor screens.
2. Description of the Related Art
In the conventional kind of video signal processing apparatus 1 shown in FIG. 11, a plurality of video signals from cameras 0 to 15 are applied to switches 2a and 2b included in a time-division multiplex circuit 1a and switches 2c and 2d included in a multi-display circuit 1b such that any video signals are selected by control signals "cmfx", "cmfy", "cmmx" and "cmmy" outputted from switch control circuits 3a and 3b. Video signals selected by the switches 2a and 2b are converted into digital video signals by A/D converters 4a and 4b, and then inputted to memories 5a and 5b, each of which has a memory capacity equal to one field, and portions of the video signals, each of which is equal to one field, are written into the memories 5a and 5b, respectively. The video signals read-out from the memories 5a and 5b are multiplexed by a multiplexer 7a, whereby a time-division multiplex video signal is obtained.
In contrast, the video signals outputted from the switches 2c and 2d and converted into digital video signals by A/D converters 4c and 4d are written into any areas of a plurality of memory formed in memories 5c and 5d through selectors 6c and 6d. Then, sixteen (16) video signals read-out from the memories 5c and 5d are outputted to a monitor (not shown) through a multiplexer 7d and a D/A converter. Therefore, sixteen video images are simultaneously displayed on sixteen monitor screens in the monitor.
The switch control circuits 3a and 3b have the structure as that shown in FIG. 12. A reference pulse "vd" is inputted to respective counters 8a and 8b as an enable signal. Count values incremented by the enable signals are outputted from the counters 8a and 8b as control signals "cmfb" and "cmmb", and the control signal "cmfb" is applied to latch circuits 9a and 9b, and the control signal "cmmb" is applied to latch circuits 9c and 9d. Each of the latch circuits 9a to 9d is constituted by D-type flip-flop circuits of four (4) bits, and the control signals "cmfx", "cmfy", (commx) and "cmmy" which control the switch circuits 2a to 2d are outputted from the latch circuits 9a to 9d, respectively.
A timing chart of an operation according to the related art is shown in FIG. 13. The switch control circuit 3a outputs the control signals "cmfx" and "cmfy" which are incremented by two (2) at every two fields and have a phase difference equal to one field, as shown in FIGS. 13(D) and 13(H). Accordingly, the video signals shown in FIGS. 13(I) and 13(J) are outputted from the A/D converters 4a and 4b, and written into the memories 5a and 5d. The video signals read-out from the memories 5a and 5b are multiplexed by the multiplexer 7a, and therefore, the time-division multiplex video signal that the respective video signals are changed at every one field as shown in FIG. 13(K) is outputted from an output terminal.
In contrast, the switch control circuit 3b included in the multi-display circuit 1b also outputs the control signals "cmmx" and "cmmy" which are incremented by two (2) at every two field and have a phase difference equal to one field, as shown in FIGS. 13(M) and 13(N). Accordingly, the video signals outputted from the A/D converters 4c and 4d at timings shown in FIGS. 13(O) and 13(P) are written into the memories 5c and 5d, and then, the sixteen video signals are read-out from the memories 5c and 5d. Therefore, the monitor screens corresponding to the video signals shown in the FIG. 13(Q) are renewed.
However, since a renewal speed of the monitor screens depends on the number of the A/D converters provided in the multi-display circuit, it is necessary to increase the number of A/D converters in order to increase the renewal speed.